The invention can for example be implemented in a high-density neuromorphic circuit for the emulation of large biological neural networks, such as those described in the following publications:                “Wafer-scale integration of analog neural networks”, by J. Schemmel, J. Fieres, and K. Meier, IJCNN, 2008, and        “Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses”, by Vogelstein R J, Mallik U, Vogelstein J T and Cauwenberghs G., IEEE Transactions on Neural Networks, 2007, 18(1): 253-265.        
The invention can furthermore for example be implemented in a high-density neuromorphic circuit for signal processing applications (image, video, audio), classification via learning, intelligent retina.
Other applications are possible.
The invention in particular relates to “spiking neurons”. These neurons are basic processing circuits intended to be linked, which behave as temporal integrators with leakage. Their internal potential reflects the sum of the various positive or negative inputs received with the passing of time, subjected to a leakage often modelled by a constant leakage current. When the internal potential of the neuron reaches a certain threshold, the neuron signals this event via a logic and electrical event of short duration (equivalent to an action potential for the biological neuron). Its internal potential then returns to its idle value, on standby for future new contributions of inputs. This logic event will in turn, through the intermediary of its electrical manifestation, generate an input in the post-synaptic neurons connected to the source neuron.
However, an analogue spiking neuron requires a large-size capacitor element (capacitance of a magnitude of 500 fF) in order to carry out the temporal integration of the weighted input signals, which consumes substantial silicon surface.